Signals in a NAND gate


Can anyone please tell me the answer for: Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

Asked By: sekhar
On: Dec 12, 2004 12:10:38 AM

Comments(4)



naman plz answer clearly the above concept, iam getting confused.
hey shekhar thanks firtof all for the refernce that u gave to me for faqs. now the question to you answer lies partly in the above comment by acrosbug. we should connect nmos A Lclose to the gnd terminal or say the source of A actually goes to the VSS terminal(to be specific). doing this actually reduces the treshlod voltage of nmos A since its source is connected to gnd, so it gets turned on faster...thus instead of havig B near the o/p we would have A.doing this would actually result in a steeper vlotage transfer characterstic, thus increased noise mairgins. note this is in case of an nmos....in case of pmos the conditions can change...if we are talking about the changing input pattern.
Hi, Thank you. Sekhar
Connect the signal that arrives first to the transistor that is nearer to vdd/vss. In this case, the parasistic capacitance is discharged before the next signal arrives. By the time, the next signal arrives, it directly switch on/off your output without having to discharge the parasistic C. Thus, min delay.
You have to be logged in to be able to post a comment. To login Click Here. First time? Signup It just takes a few minutes to sign up.
Members with Most Replies
Find Job Openings