Signals in a NAND gate
Can anyone please tell me the answer for:
Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
Asked By: sekhar
On:
Dec 12, 2004 12:10:38 AM
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Comment By: anjani
On: Jan 3, 2005 6:23:50 AM