how to display counter on LCD

This works for me in spartan 3E FPGA having clock of 50 MHz.Try this...... ----------------------------------------------------------------------------------- -- one digit BCD counter ----------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY BCD_counter IS PORT(clc,clk,ceu : IN std_logic; tc10u : OUT std_logic; -- terminal count u : OUT std_logic_vector(3 DOWNTO 0) ); END BCD_counter; ARCHITECTURE FSM_style OF BCD_counter IS SIGNAL present_state_u, future_state_u : std_logic_vector(3 DOWNTO 0); BEGIN -- Units counter ******************************************************************* -- State register, normally synthesized by D-type FF's state_register_u: PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN present_state_u <= future_state_u; END IF; END PROCESS state_register_u; -- CS1: combinational logic for determining the next state CS1_u: PROCESS (present_state_u, ceu, clc) BEGIN IF clc = '1' THEN future_state_u <= "0000"; ELSIF ceu = '0' THEN future_state_u <= present_state_u; ELSIF present_state_u = "1001" THEN future_state_u <= "0000"; ELSE future_state_u <= present_state_u + 1; END IF; END PROCESS CS1_u; -- CS2: combinational logic to determine the outputs -- CS2_u: tc10u <= '1' WHEN (present_state_u = "1001" AND ceu = '1') ELSE '0'; u <= present_state_u; -- *************************************************End of units counter END FSM_style ; ---------------------------------------------------------------------------------------------------- --- Defing OR Gate ---------------------------------------------------------------------------------------------------- library IEEE ; use IEEE.STD_LOGIC_1164.ALL ; use IEEE.STD_LOGIC_ARITH.ALL ; use IEEE.STD_LOGIC_UNSIGNED.ALL ; entity ORGate is port(a,b:in std_logic; y :out std_logic); end ORGate; architecture behavioral of ORGate is begin y <= a or b; end behavioral; ------------------------------------------------------------------------------------------------------- -- Defing And Gate ------------------------------------------------------------------------------------------------------- library IEEE ; use IEEE.STD_LOGIC_1164.ALL ; use IEEE.STD_LOGIC_ARITH.ALL ; use IEEE.STD_LOGIC_UNSIGNED.ALL ; entity AndGate is port(x,w:in std_logic; z :out std_logic); end AndGate; architecture behavioral of AndGate is begin z <= x and w; end behavioral; --------------------------------------------------------------------------------------------------- -- --------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -- Module Name: ClockGenerator - Behavioral ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity div_clk is port( clk :in std_logic; rst :in std_logic; clk_div :out std_logic); end div_clk; architecture Behavioral of div_clk is signal cnt : integer; signal temp : std_logic; begin process(clk,rst) begin if(rst='1') then temp <= '0'; cnt <= 0; elsif(clk'event and clk='1') then if(cnt= 33899999) then temp <= not temp; cnt <= 0; else cnt <= cnt +1 ; end if; end if; end process; clk_div <= temp; end Behavioral; ------------------------------------------------------------------------------------------------------- -- Defing component ------------------------------------------------------------------------------------------------------- library IEEE ; use IEEE.STD_LOGIC_1164.ALL ; use IEEE.STD_LOGIC_ARITH.ALL ; use IEEE.STD_LOGIC_UNSIGNED.ALL ; package my_component is component BCD_counter is PORT(clc,clk,ceu : IN std_logic; tc10u : OUT std_logic; -- terminal count u : OUT std_logic_vector(3 DOWNTO 0)); END component; component ORGate is port(a,b:in std_logic; y :out std_logic); end component; component AndGate is port(x,w:in std_logic; z :out std_logic); end component; component div_clk is port(clk :in std_logic; rst :in std_logic; clk_div :out std_logic); end component; end my_component; ------------------------------------------------------------------------------------------------------- --- Defining Three Digit BCD Counter ------------------------------------------------------------------------------------------------------- library IEEE ; use IEEE.STD_LOGIC_1164.ALL ; use IEEE.STD_LOGIC_ARITH.ALL ; use IEEE.STD_LOGIC_UNSIGNED.ALL ; use work.my_component.all; entity BCD_3 is port(clk,ce,R:in std_logic; u,t,h:out std_logic_vector(3 downto 0)); end BCD_3; architecture behavioral of BCD_3 is signal z1,z2,z3,z4,tc10u,tc10t,tc10h,ceh: std_logic; signal clc:std_logic :='1'; signal clk_div:std_logic; begin p2:component div_clk port map(clk,'0',clk_div); B1:component BCD_counter port map(clc,clk_div,ce,tc10u,u); -- unit place A1:component AndGate port map(tc10u,ce,z1); B2:component BCD_counter port map(clc,clk_div,z1,tc10t,t); -- tenth place A2:component AndGate port map(tc10t,ce,z2); A3:component AndGate port map(z2,z1,ceh); B3:component BCD_counter port map(clc,clk_div,ceh,tc10h,h); -- hundred place A4:component AndGate port map(tc10t,tc10h,z3); A5 :component AndGate port map(z1,z3,z4); O1:component ORGate port map(R,z4,clc); end behavioral; --------------------------------------------Package--------------------------------------------------- library IEEE ; use IEEE.STD_LOGIC_1164.ALL ; use IEEE.STD_LOGIC_ARITH.ALL ; use IEEE.STD_LOGIC_UNSIGNED.ALL ; package my_package is component BCD_3 is port(clk,ce,R:in std_logic; u,t,h:out std_logic_vector(3 downto 0)); end component; end my_package; ------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.my_package.all; entity lcd_6 is Port ( clk,rst,ce : in STD_LOGIC; sf_ce0 : out STD_LOGIC; rs : out STD_LOGIC; rw : out STD_LOGIC; en : out STD_LOGIC; out0,out1,out2,out3 : out STD_LOGIC); end lcd_6; architecture Behavioral of lcd_6 is signal ossz : STD_LOGIC_VECTOR (5 downto 0); signal ora : STD_LOGIC := '0'; signal lcd_stb : STD_LOGIC := '0'; signal lcd_stuff : STD_LOGIC_VECTOR (6 downto 0) := "0000000"; signal count : STD_LOGIC_VECTOR(26 downto 0) := "000000000000000000000000000"; signal b: STD_LOGIC := '1'; signal Q1,Q2,Q3:STD_LOGIC_VECTOR(3 downto 0):="0000"; begin Q:COMPONENT BCD_3 PORT MAP(CLK,CE,RST,Q1,Q2,Q3); process (clk) begin if clk'event and clk='1' then count <= count + 1; sf_ce0 <= '1'; case (count(25 downto 20)) is when "000000" => ossz <= "000011"; --X"03" when "000001" => ossz <= "000011"; --X"03" when "000010" => ossz <= "000000"; --X"03" when "000011" => ossz <= "000010"; --X"02" when "000100" => ossz <= "000010"; --X"02" function set when "000101" => ossz <= "001000"; --X"08" when "000110" => ossz <= "000000";-- X"00" entry mode when "000111" => ossz <= "000110"; --X"06" when "001000" => ossz <= "000000"; -- display on/off when "001001" => ossz <= "001100"; when "001010" => ossz <= "000000"; -- display clear when "001011" => ossz <= "000001"; when "001100" => ossz <= "000000"; -- Take cursor home when "001101" => ossz <= "001111"; when "001110" => ossz <= "100011"; -- Drive with the counter o/p when "001111" => ossz(5 downto 4) <= "10"; ossz(3 downto 0) <= Q3; when "010000" => ossz <= "100011"; when "010001" => ossz(5 downto 4) <= "10"; ossz(3 downto 0) <= Q2; when "010010" => ossz <= "100011"; when "010011" => ossz(5 downto 4) <= "10"; ossz(3 downto 0) <= Q1; when "010100" => ossz <= "101011"; when "010101" => ossz <= "100000"; -- ossz(3 downto 0) <= Q1; when "010110" => ossz <= "100100"; when "010111" => ossz <= "101000";-- H when "011000" => ossz <= "100100"; when "011001" => ossz <= "100101";-- E when "011010" => ossz <= "100100"; when "011011" => ossz <= "101100";-- L when "011100" => ossz <= "100100"; when "011101" => ossz <= "101100";-- L when "011110" => ossz <= "100100"; when "011111" => ossz <= "101111";-- O when "100000" => ossz <= "101010"; when "100001" => ossz <= "100000";-- when "100010" => ossz <= "100101"; when "100011" => ossz <= "100111";-- W when "100100" => ossz <= "100100"; when "100101" => ossz <= "101111";-- O when "100110" => ossz <= "100101"; when "100111" => ossz <= "100010";-- R when "101000" => ossz <= "100100"; when "101001" => ossz <= "101100";-- L when "101010" => ossz <= "100100"; when "101011" => ossz <= "100100";-- D when "101100" => ossz <= "100100"; when "101101" => ossz <= "100100";-- D when others => ossz <= "010000"; end case; if ora='1' then ora <= '0'; else ora <= '1'; end if; b <= count(19) or count(18); lcd_stb <= b and NOT ossz(4); lcd_stuff(6) <= lcd_stb; lcd_stuff(5 downto 0) <= ossz; (en, rs, rw,out3,out2,out1,out0 ) <= lcd_stuff; end if; end process; end Behavioral;

thanks

hello,i want to know, how to initialized RS 20 X 2 matrix LCD