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<-- Previous Next -- > TOPIC: write a VHDL code for J-K Flip Flop & D FF
Posted by: bobbysingh     11/14/2007 2:46:55 AM     Category: VHDL
Questions posted: 4         Comments Posted: 0
write a VHDL code for J-K Flip Flop & D flip flop.

Posted by: yadamaa     2/25/2013 11:36:25 PM
Comments Posted:2       

Thanks


Posted by: yadamaa     2/25/2013 11:36:20 PM
Comments Posted:2       

Thanks


Posted by: djvins     1/24/2011 12:15:09 AM
Comments Posted:1       Questions Posted:1

can anyone tell me the coding for jk flipflop in dataflow method...plzz


Posted by: s.veeranna33     2/21/2008 11:48:59 PM
Comments Posted:1       Questions Posted:1

very good

thanks


Posted by: $---Jay---$     11/14/2007 5:38:11 AM
Comments Posted:104       Questions Posted:1

hope it'll give u the answers...

****************
d-ff
****************
---------------------------------------------

library ieee ;
use ieee.std_logic_1164.all;
use work.all;

---------------------------------------------

entity dff is
port( data_in: in std_logic;
clock: in std_logic;
data_out: out std_logic
);
end dff;

----------------------------------------------

architecture behv of dff is
begin

   process(data_in, clock)
   begin

       -- clock rising edge

if (clock='1' and clock'event) then
   data_out <= data_in;
end if;

   end process;

end behv;

----------------------------------------------


**************
jk-ff
**************
----------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

----------------------------------------------

entity JK_FF is
port ( clock: in std_logic;
J, K: in std_logic;
reset: in std_logic;
Q, Qbar: out std_logic
);
end JK_FF;

-----------------------------------------------

architecture behv of JK_FF is

   -- define the useful signals here

   signal state: std_logic;
   signal input: std_logic_vector(1 downto 0);

begin

   -- combine inputs into vector
   input <= J & K;

   p: process(clock, reset) is
   begin

if (reset='1') then
   state <= '0';
elsif (rising_edge(clock)) then

           -- compare to the truth table
   case (input) is
when "11" =>
   state <= not state;
when "10" =>
   state <= '1';
when "01" =>
   state <= '0';
when others =>
   null;
end case;
end if;

   end process;

   -- concurrent statements
   Q <= state;
   Qbar <= not state;

end behv;

-------------------------------------------------


Posted by: unsubscribed     11/14/2007 3:24:03 AM

write VHDL code for J-K FlipFlop and D- Flip Flop




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