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TOPIC: how to draw layout of capacitor in cadence
Posted by:
vinjamoori
8/28/2007 11:45:55 AM Category: CMOS
Questions posted:
4 Comments Posted:
0
i designed one op-amp ckt
in this i have one compensation capacitor,
its value is 3pf
i want to draw layout of this capacitor in
cadence tools.
i am using .6u tech files ( gpdk files )
thankyou
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Comments Posted:1