1. In this program i have used 'addvalue' as generic. But if i change the value as say 5 it is not reflected in the output wave. Why? Right now iam using Modelsim SE simulator....

2.Does it mean that generics are not as advantageous as Constants?

3. The value of the " in1int<= conv_integer(in1);"
in the code results in a negative value what is the reason for it?

entity iob is
generic(width:positive:=3;
       addvalue:integer:=9) ;
port(rst:in std_logic;
    clock:in std_logic;
    in1:in std_logic_vector(width-1 downto 0);
    out1:out std_logic_vector(width-1 downto 0));
end iob;    

architecture iob_arch of iob is
   signal in1int:integer;
   signal sum:integer;
begin
   process(clock)
   begin
       if (clock'event and clock='1') then
           if (rst='1')then
               in1int<=0;
               sum<=0;
               out1<="000";
           else
               out1<= in1;
               in1int<= conv_integer(in1);
               sum<= in1int + addvalue;
          end if;
      end if;
end process;
end iob_arch;