what is a "timing arc"?

I don't know what it is "timing arc" in VLSI. I saw a article. it mentioned a FF has one timing arc. A LATCH has two timing arc. would you explain about "timing arc"?

Asked By: ememoho
On: Jun 13, 2007 12:34:49 PM


Thats what I meant although I should have talked about the transparency arc more. But thanks for the clarification.
ememoho, timing arc is nothing a timing path from any input to any output. For a simple FF you have inputs D & CK and output Q . Since the FF is edge triggered you have an arc from CK to Q. Since it is the clock edge that controls the output timing and D has no significance ( provided setup/hold are met) For latch you have timing path between CK and Q (when D is already stable) and also D and Q (when latch is transparent and D changes). So you can say latch has 2 arcs. spiceworks, you are partially correct.
Timing arc is the timing of data signal travelling from source FF to destination FF on rising clk edges. Timing arc of latch is timing of data travelling between rising clk edge to falling clk edge and then from falling clk edge to the next rising clk edge of the next latch. In a latch based design you have to use two latches between two consecutive rising clk edges - one latch is transparent on low clk and other is transperant on high clk. So effectively you end calculating timing between consecutive rising clk edges.
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