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<-- Previous Next -- > TOPIC: pipeline architecture
Posted by: cp.add     5/13/2007 3:39:37 PM     Category: Microprocessor
Questions posted: 1         Comments Posted: 0
what is pipeline architecture? what is speed up, efficiency and throughput of n-stage pipeline architecture over non-pipelined architecture?

Posted by: swapnja     9/17/2008 6:36:37 AM
Comments Posted:2       

u not gine me exact answer


Posted by: swapnja     9/17/2008 6:29:40 AM
Comments Posted:2       

please send me answer quickly


Posted by: santhoshvv     5/14/2007 1:27:45 AM
Comments Posted:53       Questions Posted:6

Pipelining can dramatically improve device performance by restructuring long data paths
with several levels of logic and breaking them up over multiple clocks. This method allows
for a faster clock cycle and increased data throughput at small expense to latency from
the extra latching overhead. Because FPGAs are register-rich, this is usually an
advantageous structure for FPGA design since the pipeline is created at no cost in terms
of device resources. However, since the data is now on a multi-cycle path, special
considerations must be used for the rest of the design to account for the added path
latency. Care must be taken when defining timing specifications for these paths. The
ability to constrain multi-cycle paths with a synthesis tool varies based on the tool being
used. Check the synthesis tool's documentation for information on multi-cycle paths.
Note It is recommend that careful consideration before trying to pipeline a design. While
pipelining can dramatically increase the clock speed, it can be difficult to do correctly.
Also, since multicycle paths lend themselves to human error and tend to be more
troublesome due to the difficulties in analyzing them correctly, they are not generally
recommended for reusable modules.




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