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<-- Previous Next -- > TOPIC: what is FPGA gate count and what is ASIC gate
Posted by: nitin_ndg     4/20/2007 4:25:12 AM     Category: ASIC
Questions posted: 5         Comments Posted: 7
Hi
  i dont have have clear picture for gate counts.
here i have one example:
suppose i write vhdl code for

Y= ABC+ (/A)BC

1.THEN what will be my gate count for both ASIC and FPGA.?
2.what are the conditions on which gate count depends.
3. how to convert FPGA gate count to ASIC gate count



Posted by: unsubscribed     4/24/2007 3:20:59 AM

Hi ,After implementing the design. Open the schematic window in Xilinx  and see wats there .
As i said Gate count depends upon the basic logic cell Architecture .. u should read the Hardware details of the kit U use .


Posted by: mkumarmoon     4/23/2007 6:59:48 AM
Comments Posted:19       Questions Posted:6

Hi all,
I have implemented just 2 input and gate in XILINX.
It shows total no of gate count : 6
then i try one more or gate.
Now it shows 12 gates.
i have written my thoughts previously.
u pls clarify what is the meaning of gatecount in xilinx.

Regards
Muthukumar





Posted by: unsubscribed     4/22/2007 1:19:14 PM

Dont use the term transistor count .Just keep in mind that ( corrected )Gate count*4=  Trans. count. No body uses the term transistor count .



Posted by: nitin_ndg     4/22/2007 3:57:47 AM
Comments Posted:7       Questions Posted:5


hi sakthiblore

  "Every gate needs Atleast 2 transitor to be realized.
Normally Gate count = 4* Tansisitor count"

meas if transistor count is 2 say for NOT gate then gate count will we :

=> Gate count = 4* Tansisitor count
=> Gate count = 4* (2)
=> Gate count = 8; thats not correct. i think gate count should be 1 as it is NOT gate.

plz correct me if i am wrong.

regards
nitin


Posted by: unsubscribed     4/22/2007 3:40:37 AM

ya .Its true tat Nor or nand gate when realized using the universal gate(NAND)increases the gate count.But keep in mind that All the FPGAs dont use universal gates  as the Basic Logic Block.

And  u cant say Gate count = Transistor Count.Bcoz,
Every gate needs Atleast 2 transitor to be realized.
Normally Gate count = 4* Tansisitor count. Thanx .
pls. correct me if iam wrong



Posted by: mkumarmoon     4/21/2007 7:10:51 AM
Comments Posted:19       Questions Posted:6

Hi nitin,
yes,It means transister count.

Anybody disagree with this u pls clarify.

Regards
Muthukumar


Posted by: nitin_ndg     4/20/2007 12:47:05 PM
Comments Posted:7       Questions Posted:5

Hi Muthukumar
  Does the gate count means transister count?


Posted by: mkumarmoon     4/20/2007 8:57:59 AM
Comments Posted:19       Questions Posted:6

Hi nitin,

Flow of FPGA and ASIC are different.
In FPGA we donot take much care whicle verification.
In ASIC we have to take much care while designing and verification.
In gate count point of view
same meaning for the for the both.
But In FPGA No of gate counts consumed by design should be lessthan the total no of gates present in the FPGA device.
In your case
Y=ABC+(!A)BC
First it is eloborate and optimized it
Y=BC
this will take simple and gate.
But if u r implement in FPGA it shown 6 gates
Why ?
this is because of every FPGA or ASIC device designed only thrw universal gate that is NAND gate or NOR gate .
But NAND only normally used for some other reason(fanout).
In our case this and gate converted into nand gate with NOT gate .
NAND gate takes 4 transisters.
NOT gate take 2 transisters.
Now u can get the 6 gates.


Thanks and Regards
Muthukumar


Posted by: unsubscribed     4/20/2007 6:17:32 AM


If u want to implement ur design on FPGA u should make sure that the Gate-count of ur Design Should be lesser that that of the FPGA.(u can see this info. on the manual)

I dont think gate count of a design  Changes for ASIC/FPGA .


Posted by: unsubscribed     4/20/2007 6:14:41 AM


Gate count is nothing but the resources needed to implement the design Or simply u can say. Area Consumed. For eg. if u want to design a 2 i/p And gate the GAte count should  be 4 As we want 4 gates to design An gate.




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