VHDL CODE FOR CLOCK DIVIDER

HI , process(clkA, reset) begin if reset = '0' then ClkA_2 <= '0'; elsif (ClkA = '1' and ClkA'event) then ClkA_2 <= not(ClkA_2); end if; end process;

hi i just want to know whether the above code is synthesizable... i dnt thnk it wil get synthesize...

hi, clk div is very simple,just define a clk and take a counter . by using counter we can divide the clk. for example here iam giving divide by 2 clk, u can go through that and then will get an idea... entity div_clk is port( clk :in std_logic; rst :in std_logic; clk_div :out std_logic ); end div_clk; architecture Behavioral of div_clk is signal cnt : integer; signal temp : std_logic; begin process(clk,rst) begin if(rst='1') then temp <= '0'; cnt <= 0; elsif(clk'event and clk='1') then if(cnt= 2) then temp <= not temp; cnt <= 0; else cnt <= cnt +1 ; end if; end if; end process; clk_div <= temp; end Behavioral; regards, sruthi...

Simply define a clk .. use Normal Divide- by ..Tats it .. At VHDL level, theres nothing complex.