Multiplier Code in Verilog


Hi can anyone tell me how to write a code for a multiplier with two 16 bit inputs? Thanks.

Asked By: jcha188
On: Aug 18, 2004 10:38:43 PM

Comments(16)



we are trying to do the vedic multiplication using single multiplier in verilog...how can we do?and what is the code? plz do help
can any one help me with the code of 4*4 vedic multiplier
module multiply( input [15:0] x, input [15:0] y, output [32:0]z ); assign z = x * y; endmodule
module multiply( input [15:0] x, input [15:0] y, output [32:0]z ); assign z = x * y; endmodule
please give me 16bit multiplier in verilog.
Hey nethra, I got what you said and have corrected it, its working fine now. Thanks for the help, appreciate it. :) I have posted a question regarding rounding of multiplier output bits to half the total bits. (eg:-4 bits from 8). Is it possible? How? Please help me with it if you can. It would be a great assist in my project. Thanking You, Eshaan
IF statement is wrong in the code......... How do u possibly think it will work? Read the code first and understand before executing.......
Hey raiyani i gave inputs to the code you specified above and i am getting incorrect output. Final multiplied value is coming as xxxxxxxx (FOR ANY SET OF INPUTS). Here is what i added to you code: module shift_add_mul(x,y,z,reset); input [3:0] x,y; input reset; output [7:0] z; //wire co,ci; reg [7:0] t; reg [7:0] z; integer i; always @ (x or y or reset ) begin //if(reset) z = 8'b0; //j = 0; for(i = 0; i < 4 ; i = i + 1) begin t = 8'b0; if(y[i]) begin t[i] = x[0]; t[i+1] = x[1]; t[i+2] = x[2]; t[i+3] = x[3]; end z = z + t; end end endmodule module top(); reg [3:0] a,b; reg r; wire [7:0] c; shift_add_mul r1(a,b,c,r); initial begin a = 4'b0011; b = 4'b0010; r = 1'b1; $display("a=%d b=%d c=%b\n", a, b, c); end endmodule After a lot of debugging I have found that the error is in the if statement. The compiler isnt going into the if loop at all. Please look into it and help me. Thanks
hey 'm lukin complex multiplication of two numbers. plz suggest me..
module shift_add_mul(x,y,z,reset); input [3:0] x,y; input reset; output [7:0] z; //wire co,ci; reg [7:0] t; reg [7:0] z; integer i,j; always @ (x or y or reset ) begin if(reset) z = 8'b0; //j = 0; for(i = 0; i < 4 ; i = i + 1) begin t = 8'b0; if(y[i]) begin t[i] = x[0]; t[i+1] = x[1]; t[i+2] = x[2]; t[i+3] = x[3]; end z = z + t; end end this is 4 bit multiplier code u can modify for 16 bit also. it is normal change in it.
can any one tell how 2 read the data or content from memroy location
tell me 16 bit multiplier in verilog. i am doing a projrct on rsa
for signed and unsined numbers.(with verilog)
for signed and unsined numbers.(with verilog)
there r several algos for multiplication. which one u want?
What type of multiplier are you talking about ? If its a simple multiplier just input two 16 bit numbers and use multiplier operator. The Synthesis tool will use the best possible option it has for your design. Or else if you want to implement special type of multiplier you will have to use structural verilog.
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