follwing VHDL code gives  u freq divide by 3 with approx 33.333% duty cycle



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity text is
generic(n:integer:=3);
port(fin:in std_logic;
fout:out std_logic);
end text;

architecture text_arch of text is

begin
process(fin)
variable count:integer:=0;
begin
if rising_edge(fin) then



if  count = n-1  then
fout <= '1' ;
count := 0;
else
fout <= '0';
count := count + 1;
end if;

end if;
end process;
end text_arch;