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<-- Previous Next -- > TOPIC: CMOS inverter Rise Time calculation
Posted by: rajeevn     11/4/2006 7:30:25 PM     Category: CMOS
Questions posted: 5         Comments Posted: 0
Hi,

i would like to know how the intergral limits are taken for rise/fall time calculation in a cmos inverter. For calculating fall time it taken from 0.9VDD to VDD-Vtn for which NMOS is in saturation and betweem VDD-Vtn to 0.1VDD for which NMOS is in linear. Similarly, how the limits are distributed for PMOS to calculate the rise time.

2. Also, for calculating propagation delay how the integral limits are distributed for PMOS. I appreciate your response.

Thanks,
Raj

Posted by: nayeem_su     7/11/2008 1:19:47 AM
Comments Posted:1       



i would like to know how the intergral limits are taken for rise/fall time calculation in a cmos inverter. For calculating fall time it taken from 0.7VDD to VDD-Vtn for which NMOS is in saturation and betweem VDD-Vtn to 0.2VDD for which NMOS is in linear. Similarly, how the limits are distributed for PMOS to calculate the rise time.


Posted by: svhmadhuri     11/5/2006 5:24:57 AM
Comments Posted:10       

refer to the book cmos digital integrated circuits by sung-mo kang.....he had mentioned these calculations in detail.




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