wait statement.....

hi every one.... i need good examples for 'wait' statements that can be implemented and understand it in a better way... and is it possible to see the result(output) in the Xilinx or QuartusII(5.0 )/Altera..? if yes. how? if not any other way to understand it in a better way....

Asked By: sarath_c
On: Aug 2, 2006 1:32:12 AM

Comments(3)

Hi sarath,just look at the test bench and the purpose.test bench is used to verify the design. features of testbench 1.empty entity port. 2.no sensiticity list. now u may have the idea.without sentivity list how we have to start and stop the process. the only way wait statement.delay is depends upon the maximum clock frequency. if it is 100 MHz the we give 5 ns for upper level and 5 ns for lower level. hope u r understand regards muthukumar.p

Comment By: muthu_kumar
On: Aug 4, 2006 1:02:16 AM

thank u muthu_kumar.... and let me know why statements like 'wait' and 'after' are used for.....? and what if we are not using this delays.....?and how shall we know how much delay we have to give and where they shall be used? thanks, Sarath.

Comment By: sarath_c
On: Aug 2, 2006 10:01:50 PM

Hi,in my point view 1.wait statement is mainly used with in the testebench. 2.so this is only possible in simulation not synthesisation. 3.by use of modelsim u can simulate and u can see the result . regards muthukumar.p

Comment By: muthu_kumar
On: Aug 2, 2006 2:45:16 AM

You have to be logged in to be able to post a comment. To login Click Here. First time? Signup It just takes a few minutes to sign up.

Members with Most Replies

Find Job Openings

Indeed jobs