how to reduce simulation time and synthasis


1.can any one plzz tell me how to reduce simulation time???????is there any different methods to reduce simulation methods? is it possible to reduce synthsis?if possible how can we achive this? these all are interview questions... wating for u r suggestions thanks hapi

Asked By: hapi
On: May 23, 2006 8:22:20 AM

Comments(5)



hi i want to know about about synthesis process briefly . so can u plz suggest me r send me the links regarding the topic. thanks in advance satish
hi i want to know about about synthesis process briefly . so can u plz suggest me r send me the links regarding the topic. thanks in advance satish
yaa madhu, """"while designing complex designes, break the design into possible number of sub-modules under a main-module instead of writting whole code in a single module """" i think this will not help us in decreasing the synthesis time.this is beneficial for us during finding problems in our code.finding errors in large code is always dificult.so this is good approach to find problems fast during simulation or on board testing. hope i am right.
vikas u given very good response for this question one more method to optimize the synthesis time is: while designing complex designes, break the design into possible number of sub-modules under a main-module instead of writting whole code in a single module
the best method of reducing simulation time is by Senstivity list should be small to derease the simulation time.go for synchronous designs. for reducing synthesis time": define all outputs in all states in case of state machines. use recommended coding styles. use more case statement then if else because case statment is fast is better for synthesis purpose.
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