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Main EDA Embedded Systems ASIC FPGA VHDL Verilog CMOS Semiconductors DSP Mixed Signal Architecture Miscellaneous
Account Information

            Title

            Category

            Date

    Replies

    Status

    race condition
    ASIC
    5/30/2005 2:10:19 AM
    5
    Open
    timing verification
    ASIC
    5/19/2005 12:06:54 AM
    0
    Open
    book on high speed digital design
    ASIC
    5/3/2005 11:44:50 PM
    2
    Open
    Time borrowing
    ASIC
    4/22/2005 9:49:43 PM
    5
    Open

            Title

            Comments

            Accepted Comments

    difference1
    1
    0
    hold time violation venkatesh plz answer
    1
    0
    Asic
    1
    0
    How to view internal signals in post synthesi
    1
    0
    Analog and Digital
    1
    0
    Si better than Ge?
    1
    0
    Query related to CMOS Inputs - Thanks Rohit
    1
    0
    why hold time is not included in Fmax eq
    1
    0
    pls help me???
    1
    0
    race condition
    2
    0
    intervew question 6 can any one try out???
    1
    0
    book on high speed digital design
    1
    0
    USING BOTH EDGES OF A CLOCK FOR DRAM CONTROL
    1
    0
    can any one send MODELSIM software please
    1
    0
    Time borrowing
    2
    0
    Different I/O buffers in Xilinx FPGA
    1
    0
    HEX files
    1
    0
    VHDL code for iir filter, very urgent
    1
    0
    NAND Gate Optimization
    1
    0
    Post-silicon Validation
    1
    0
    D-Type Flip-Flop
    1
    0
    FPGA DSP interface
    3
    0
    tristate buffer
    1
    0
    Propagation delay
    1
    0
    impact
    1
    0
    janas sequence detector
    1
    0
    reusability
    2
    0
    message for Praveen_sam
    1
    0
    Altera MAX+plus2 you make me anger
    1
    0
    FPGA Bit file
    1
    0
    Interfacing DIO2 to D2-SB
    1
    0
    FPGA design tools
    2
    0
    How to work on CANDENCE
    1
    0
    vhdl or verilog
    1
    0
    Altera MAXplus, you make me anger
    2
    0
    SRAM working
    1
    0
    how to download vhdl code on fpga
    1
    0
    handling interrupts
    1
    0
    Standard cell vs GAte array
    1
    0
    PMOS pull up transistors
    1
    0
    0.13u technology
    1
    0
    SIGNALS
    1
    0
    how body effect deermines no of transistor in
    1
    0
    IBM Power PC 970 FX RISC Proc.
    1
    0
    fault tolerent state machine.
    1
    0
    Look Up Table
    1
    0
    Gate Count
    1
    0
    Netlist
    1
    0
    sattellite communication
    1
    0
    Difference between a GATE ARRAY and a FPGA?
    1
    0
    DIFFERENCE BETWEEN FPGA &ASIC
    2
    0
    Power Optimising techniques in FPGAs
    1
    0
    subthreshold cur
    1
    0
    vlsi technology
    1
    0
    result of swapping n and pmos in a inverter
    2
    0
    Difference beteween FPGA & CPLD?
    1
    0
    what r the uses of transmission gates?
    1
    0
    metal layers
    1
    0
    vias
    1
    0
    -ve edge triggered ff
    1
    0
    Parameters affected by decreasing the length
    1
    0

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Users with most replies

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$---jay---$
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