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Main EDA Embedded Systems ASIC FPGA VHDL Verilog CMOS Semiconductors DSP Mixed Signal Architecture Miscellaneous
Account Information

            Title

            Category

            Date

    Replies

    Status

    keeper circuit
    FPGA
    7/17/2006 1:30:49 AM
    3
    Open
    wire and reg
    Verilog
    7/15/2006 12:52:28 AM
    5
    Open
    back end and front end
    FPGA
    6/22/2006 11:09:57 PM
    3
    Open
    core voltage
    FPGA
    6/20/2006 11:40:56 PM
    2
    Open
    asic devices
    ASIC
    6/20/2006 11:39:37 PM
    3
    Open
    DFT?
    ASIC
    6/19/2006 5:46:59 AM
    1
    Open
    sync Vs asyn
    FPGA
    6/15/2006 2:54:04 AM
    2
    Open
    fanout
    CMOS
    6/14/2006 4:52:50 AM
    5
    Open
    verification tools
    ASIC
    6/14/2006 4:49:29 AM
    2
    Open
    slew rate?
    FPGA
    6/14/2006 4:48:17 AM
    3
    Open
    synthisizable or not?
    VHDL
    6/14/2006 4:46:24 AM
    10
    Open
    clock signal
    VHDL
    6/3/2006 12:34:18 AM
    1
    Open
    compare vhdl and verilog
    VHDL
    6/2/2006 5:39:10 AM
    4
    Open
    buffer and inverter
    CMOS
    6/2/2006 5:23:47 AM
    2
    Open

            Title

            Comments

            Accepted Comments

    vhdl code 4 USART
    1
    0
    rocket io
    1
    0
    7402
    1
    0
    difference bw wire/reg
    1
    0
    clock slew
    1
    0
    question in VHDL
    2
    0
    what is configuration file
    1
    0
    difference between fpga and asic
    1
    0
    digital electronics
    1
    0
    wait statement.....
    2
    0
    interview question for all
    1
    0
    Characterization
    4
    0
    CLBs
    1
    0
    ABOUT USART
    1
    0
    serial port interfacing with FPGA(VHDL code)
    1
    0
    speed of fpga design
    1
    0
    parity bits in bolck ram
    1
    0
    distributed RAM
    1
    0
    block RAM
    1
    0
    vhdl kiran
    1
    0
    while coding fsm's.......which methos is sug.
    1
    0
    if we code a case statement,what hardware....
    1
    0
    SYNCHRONOUS FIFO
    2
    0
    Obsolete CPLDs
    1
    0
    speed grade
    3
    0
    TRIANGULAR WAVE GENERATOR IN VHDL CODE
    3
    0
    keeper circuit
    1
    0
    SEMINAR ON VLSI
    1
    0
    Which is better??
    3
    0
    File access through Verilog
    1
    0
    16 * 16 one cycle multiplier
    1
    0
    vhdl and xilinx
    1
    0
    sinewave generating using VHDL code
    1
    0
    difference b/n synchronous and asynch adder
    1
    0
    fan in and fan out
    1
    0
    Sine/Cosine generator using Verilog/VHDL
    1
    0
    pipelining + throughput + letency
    2
    0
    About ASIC design
    1
    0
    back end and front end
    1
    0
    HELP!!! need answer for this interview Q
    1
    0
    digi
    1
    0
    core voltage
    1
    0
    asic devices
    1
    0
    DFT?
    1
    0
    fast multiplier
    1
    0
    fanout
    2
    0
    slew rate?
    1
    0
    synthisizable or not?
    1
    0
    sdram interface to vlsi
    2
    0
    sine cos in verilog source code plz
    4
    0
    about basic question
    1
    0
    Please help me to answer this question
    1
    0
    cmos buffer working:help me
    1
    0
    why do we break feedback during design of lat
    1
    0
    ofdm transmiter
    1
    0
    abt settling time
    1
    0
    Digital ASIC design
    1
    0
    about Asics
    1
    0

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