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            Category

            Date

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    BUILT IN SELF TEST FOR RAM
    VHDL
    8/7/2010 2:00:11 AM
    0
    Open
    CAN
    Embedded Systems
    8/3/2010 12:53:36 AM
    0
    Open
    LATENCY
    VHDL
    7/25/2010 1:01:41 PM
    1
    Open

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    VHDL prob
    1
    0

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