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Account Information

            Title

            Category

            Date

    Replies

    Status

    Analog and Digital
    CMOS
    6/8/2005 2:07:36 AM
    7
    Open

            Title

            Comments

            Accepted Comments

    significane of output and input impedance
    1
    0
    Simulation Types
    1
    0
    clock skew, clock tree
    1
    0
    delays in verilog
    1
    0
    output impedance of common source amplifier
    1
    0
    CMOS Body Effect
    1
    0
    cascaded buffers
    1
    0
    setup & hold time
    1
    0
    fsm doubt
    1
    0
    wipro motorola interview questions.plz help!!
    1
    0
    1x2 MUX for serial communication devices
    2
    0
    energy conservation on charge sharing
    1
    0
    see following quesiton asked in interview
    1
    0
    analog layouts--- p+ poly resis prefered ???
    1
    0
    plz help!
    2
    0
    Hold time relation to maximum frequency
    1
    0
    internal node capacitances in cmos
    2
    0
    prop delay of ff/ -ve setup and hold time
    2
    0
    some problems plz help!
    1
    0
    plz help! some problems
    1
    0
    Clock divide
    1
    0
    hold time in digital circuits n some bjt prob
    1
    0
    TRANSISTOR SIZING/ PULLUP RESISTENCE OF nand
    1
    0
    capacitor
    1
    0
    latency time/ small signal BJTs
    1
    0
    Vlsi interview questions
    1
    0
    Interview questions
    1
    0
    t flip flop ambiguity
    1
    0
    full power bandwidth in opamps
    1
    0
    self loading in CMOS
    1
    0
    Depth in FIFO's
    1
    0
    Latch and set up / hold time
    1
    0
    Analog and Digital
    1
    0
    Si better than Ge?
    1
    0
    Initial statements in Verilog
    1
    0
    Query related to CMOS Inputs - Thanks Rohit
    1
    0
    Query related to CMOS Inputs
    1
    0
    optimize delay
    1
    0
    how to fix a hold
    1
    0
    pls help me???
    1
    0
    Shorted Input and Output of a dummy Inverter
    1
    0
    cmos nand gate
    3
    0
    setup hold time related
    1
    0
    SLACK - Meaning ?
    1
    0
    interview question
    1
    0
    Mux O/P For X
    1
    0
    how to implement LUT(lookup table) in Verilog
    1
    0
    XOR gate implimentation using CMOS
    1
    0
    NAND
    1
    0
    design a circuit
    1
    0
    Sense Amplifier
    1
    0
    Oxide properties on frequency
    3
    0
    OPAMP
    1
    0
    Timing Analysis
    1
    0
    Hold Time in two clock domains
    1
    0
    frequency dependancy
    2
    0
    Documents for CMOS
    1
    0
    what is the diff. in ac and dc gnd in cmos
    2
    0
    Intel Interview Que.
    1
    0
    Transistor Sizing (Intel Interview)
    1
    0
    input switching voltage of 2 input nor gate
    1
    0
    Capacitor
    1
    0
    NAND Gate Optimization
    1
    0
    VERY INTERESTING PROBLEM IN 8051
    1
    0
    Connect a birdirection port in module
    1
    0
    CMOS current mirror
    1
    0
    Odd Pulse Divider Design
    1
    0
    Negative Hold time
    1
    0
    c
    1
    0
    MOS. semiconductors
    1
    0
    Pull Up transistor
    1
    0
    "Long channel vs short channel device"
    1
    0
    Convert XOR to XNOR
    1
    0
    2 input MUX
    2
    0
    generation of nand
    1
    0

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