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“There's two possible outcomes: if the result confirms the hypothesis, then you've made a discovery. If the result is contrary to the hypothesis, then you've made a discovery.”
— Enrico Fermi (1901-1954)

CATEGORY:    CMOS

            Title

            Asked by

            Date

  How to clip response of LC oscillator?
    anindya1012
   9/1/2010 1:31:03 AM
  stick diagram for 2:1 multiplexer
    bindhupearl
   8/25/2010 9:43:38 AM
  mtcmos
    sarad
   8/9/2010 8:24:13 AM
  2D DCT DESIGN IN IC STUDIO
    anilkumar11
   8/2/2010 1:35:12 AM
  cmos design challenges in the Nanotechnology era
    divyashilpa
   7/27/2010 5:46:35 AM
  leakage power in submicron technology
    janakirani
   6/19/2010 1:12:50 PM
  design low power level shifter with domino logic
    brar
   6/3/2010 1:04:48 PM
  effect
    saurabh89
   4/25/2010 8:39:34 AM
  BJT vs. MOSFET gain comparison
    anex
   4/3/2010 4:25:07 AM
  how to use hspice to know the all of the leakage
    shandabogo
   3/17/2010 11:15:15 PM
  SERF ADDER USING CMOS
    pankajnegi
   3/2/2010 11:00:40 AM
  32nm CMOS Models
    shobak101
   3/2/2010 4:15:10 AM
  low power consume
    bmprabhu16
   3/1/2010 11:41:51 PM
  Measurement of Vth in CMOS using HSPICE
    META
   12/26/2009 2:35:20 AM
  what are the symmetric signaling schemes
    hari kumar
   12/18/2009 7:55:39 AM
  PTM module in (*.pm format)
    santoshchini
   12/2/2009 1:34:25 PM
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            Title

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     Comment Date

  NMOS & PMOS
    7
   nagarajann
   8/18/2010 8:42:18 PM
  kmap
    2
   tapansahu
   8/14/2010 11:30:00 AM
  3-stage ring oscillator design in 90nm node
    2
   haribabu448
   8/8/2010 4:08:49 AM
  how to draw layout of capacitor in cadence
    3
   jsimha
   7/29/2010 5:22:32 AM
  Current Mirror vs. Current Source
    2
   anex
   6/27/2010 6:06:52 AM
  IMPORTANCE OF CMOS IN COMPUTERS
    2
   tummyl
   6/19/2010 10:58:40 AM
  network on chip
    1
   muruku
   6/15/2010 8:51:08 AM
  invention of transmission gate
    2
   gabi71ro
   6/10/2010 5:12:01 PM
  leakage power in digital cmos circuits
    4
   gabi71ro
   6/10/2010 5:08:12 PM
  low power dissipation in CMOS
    2
   gabi71ro
   6/10/2010 4:50:34 PM
  LEVEL SHIFTER
    2
   brar
   6/3/2010 1:09:31 PM
  cascaded buffers
    3
   arunbuddy36
   5/19/2010 12:45:39 AM
  Why nMOS pass Strong '0' and degraded '1'?
    1
   akif66
   5/8/2010 8:10:37 PM
  frequency dependancy
    6
   KumarSG
   4/28/2010 7:02:25 AM
  "Pass Transistor"
    6
   muruku
   4/8/2010 4:31:33 AM
  twin well process
    1
   hitesh_pra
   4/1/2010 7:04:10 AM
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