VLSIBank · Investing your Knowledge

Main EDA Embedded Systems ASIC FPGA VHDL Verilog CMOS Semiconductors DSP Mixed Signal Architecture Miscellaneous

“You cannot have a proud and chivalrous spirit if your conduct is mean and paltry; for whatever a man's actions are, such must be his spirit.”
— Demosthenes (384 BC - 322 BC)

Title

Category

Date

vhdlcode4 Fuzzy based PIDController4transportation

VHDL

7/30/2010 4:25:55 AM

how to view layout in cadence virtuoso with lef?

EDA

7/29/2010 11:47:38 AM

FPGA & ASIC

FPGA

7/29/2010 5:38:37 AM

Started with embedded

Embedded Systems

7/29/2010 2:31:26 AM

cmos design challenges in the Nanotechnology era

CMOS

7/27/2010 5:46:35 AM

lhld

Architecture

7/24/2010 9:05:11 AM

how to change baudrate ranges from 9600 to 19200

Verilog

7/23/2010 6:45:40 AM

Reconvergence

EDA

7/23/2010 2:16:55 AM

help in reading a large text file using verilog...

EDA

7/22/2010 1:52:58 AM

PRBS checker module in Verilog

Verilog

7/21/2010 4:46:36 PM

vhdl code to interface fpga with lcd

VHDL

7/21/2010 11:19:10 AM

single wire radiation

Miscellaneous

7/20/2010 2:17:54 AM

FIFO Depth Means wat.?

EDA

7/19/2010 12:15:50 AM

code for a transfer function

VHDL

7/18/2010 11:45:47 PM

7490 counter

Architecture

7/17/2010 6:47:32 AM

increment the memory

Verilog

7/16/2010 7:43:54 AM

page 1 -->

Title

Category

Last Comment by

Comment Date

divide by n counter vhdl code

VHDL

jrrahul.pand

7/29/2010 9:21:49 AM

about vhdl and vlsi

EDA

ydamod01

7/29/2010 8:56:16 AM

how to draw layout of capacitor in cadence

CMOS

jsimha

7/29/2010 5:22:32 AM

verilog code for serial to parallel converter

Verilog

gundar

7/28/2010 2:16:09 PM

VHDL prob

VHDL

gangadhar

7/28/2010 6:51:52 AM

guidenes

VHDL

lal87

7/28/2010 2:13:19 AM

LATENCY

VHDL

lal87

7/28/2010 2:10:15 AM

Are real nos in VHDL synthesizable???

VHDL

lal87

7/28/2010 2:08:42 AM

vhdl code for pn sequence generator

VHDL

lal87

7/28/2010 2:04:31 AM

sin and cosine vhdl code

VHDL

lal87

7/28/2010 2:03:57 AM

Compilation and simulation warning

Verilog

jasonkee111

7/26/2010 10:38:16 PM

Unable to simulate a waveform

Verilog

kumarshravan

7/26/2010 7:30:13 AM

verilog code pass transister

Verilog

kumarshravan

7/26/2010 6:59:32 AM

D Flip Flop/ Latch

Verilog

kumarshravan

7/26/2010 5:10:36 AM

fix the bug in the code

Verilog

kumarshravan

7/26/2010 5:01:48 AM

GATE 2008 CSE/IT

Miscellaneous

p.priyadarsi

7/26/2010 2:56:33 AM

page 1 -->

Signup Forgot Password?

Users with most replies

User

No. of Replies

$---jay---$

100

venkateshr

bharath_kt

muthu_kumar

praveen_sam

ngasm

jeppe

avvaru_theja

vikas