vlsibank

Log in or Sign up.
Main EDA Embedded Systems ASIC FPGA VHDL Verilog CMOS Semiconductors DSP Mixed Signal Architecture Miscellaneous
“We must not forget that when radium was discovered no one knew that it would prove useful in hospitals. The work was one of pure science. And this is a proof that scientific work must not be considered from the point of view of the direct usefulness of it. It must be done for itself, for the beauty of science, and then there is always the chance that a scientific discovery may become like radium, a benefit for humanity. ”
— Marie Curie (1867 - 1934)

            Title

            Category

            Date

  design & physical compiler
    EDA
   2/3/2012 9:29:53 AM
  image processing using vlsi
    EDA
   2/2/2012 11:02:52 PM
  domain of VLSI
    EDA
   2/2/2012 10:37:26 PM
  jtag boundary scan tap controller
    VHDL
   2/2/2012 2:05:31 AM
  vhdl code for (7,4) binary cyclic codes
    VHDL
   2/1/2012 6:54:09 AM
  What is the need of a Synthesizer
    FPGA
   1/18/2012 1:57:33 AM
  vlsi project
    EDA
   1/9/2012 10:07:15 AM
  vhdl code for pn sequance generator
    VHDL
   12/30/2011 9:15:28 AM
  SAT SOLVER
    Verilog
   12/30/2011 7:50:40 AM
  paralled peripheral interface8255
    Architecture
   12/26/2011 11:02:04 PM
  paralled peripheral interface 8255 using VHDL
    VHDL
   12/26/2011 10:56:23 PM
  Metastability removal using fuzzy logic
    Semiconductors
   12/23/2011 6:02:58 AM
  CADENCE POWER ANALYSIS
    EDA
   12/23/2011 3:13:33 AM
  NBTI
    CMOS
   12/22/2011 12:01:22 AM
  Magic tool tech file selection
    ASIC
   12/13/2011 10:41:54 AM
  Design of Edge Detection Systems
    VHDL
   12/12/2011 8:20:49 AM
page 1 -->

            Title

    Category

  Last Comment by

     Comment Date

  vedic multiplication
    VHDL
   prasad1987
   2/5/2012 2:10:11 AM
  Using vedic multiplier, i want to increase the spe
    Verilog
   prasad1987
   2/5/2012 12:38:38 AM
  implementation of usart using vhdl
    VHDL
   m.pandidivya
   2/4/2012 5:23:35 AM
  counter in verilog
    Verilog
   nethra_k
   2/2/2012 10:21:54 AM
  how to partition an digital circuits
    Verilog
   renoz
   2/2/2012 9:41:33 AM
  Why nMOS pass Strong '0' and degraded '1'?
    CMOS
   cutesmile
   1/30/2012 5:59:39 AM
  problem in verilog coding
    Verilog
   9273459054
   1/27/2012 8:43:00 PM
  u.p 8085
    Architecture
   e2mohd
   1/22/2012 10:32:10 AM
  DIFFERENCE BETWEEN THE SIMULATION AND SYNTHESIS
    FPGA
   nethra_k
   1/18/2012 4:05:50 AM
  power static in HSPICE
    EDA
   nethra_k
   1/11/2012 11:09:31 PM
  vhdl coding for integrator
    VHDL
   satothsa
   1/8/2012 9:52:38 PM
  Need VHDL code for an Alarm Clock
    VHDL
   nethra_k
   1/6/2012 4:54:11 AM
  Adder Implementation
    ASIC
   dolpa
   1/5/2012 6:34:06 AM
  SRAM Designing
    CMOS
   nethra_k
   1/3/2012 2:01:50 AM
  leakage power clalculator
    CMOS
   chandarpriya
   12/30/2011 7:54:17 AM
  how to Partition the digital circuits?
    Verilog
   chandarpriya
   12/30/2011 7:49:43 AM
page 1 -->

Login to access the site

  Username:
  Password:
   Signup Forgot Password?    

Users with most replies

   User
 No. of Replies
nethra_k
176
$---jay---$
104
venkateshr
86
muthu_kumar
76
bharath_kt
75
praveen_sam
70
ngasm
63
jeppe
61
avvaru_theja
57